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Silicon Labs /Series1 /EFR32MG13P /EFR32MG13P732F512IM48 /CSEN /TIMCTRL

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Interpret as TIMCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DIV1)PCPRESC 0PCTOP0WARMUPCNT

PCPRESC=DIV1

Description

Timing Control

Fields

PCPRESC

Period Counter Prescaler

0 (DIV1): The period counter clock frequency is LFBCLKCSEN/1

1 (DIV2): The period counter clock frequency is LFBCLKCSEN/2

2 (DIV4): The period counter clock frequency is LFBCLKCSEN/4

3 (DIV8): The period counter clock frequency is LFBCLKCSEN/8

4 (DIV16): The period counter clock frequency is LFBCLKCSEN/16

5 (DIV32): The period counter clock frequency is LFBCLKCSEN/32

6 (DIV64): The period counter clock frequency is LFBCLKCSEN/64

7 (DIV128): The period counter clock frequency is LFBCLKCSEN/128
PCTOP

Period Counter Top Value
WARMUPCNT

Warmup Period Counter

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data